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SUMMARY
Technology scaling has reached a point at which process and environmental variability are no longer negligible. With every new technology generation the behavior of CMOS devices becomes less predictable. Process variability, aging, sensibility to radiation, etc. lead to bit flips on register-transfer level. New approaches are required which allow building reliable systems on an unreliable hardware. This project focuses its research on hardware-reliability in wireless communication systems. The team follow a cross-layer approach which exploits the mutual trade-offs of system performance, hardware reliability, and implementation complexity. Wireless systems are especially suited for this approach because they have an inherent algorithmic error resilience.
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SOLUTIONS
- Developing a novel cross-layer methodology to guarantee reliable system behaviour on unreliable hardware
- Discovering how physical defects project themselves on register-transfer level
- Simulating bit flips on gate level and discovering their impact on the system
- Identifying and implementing low-complexity resilience actuators
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LINK:http://spp1500.itec.kit.edu/286_297.php
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